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drpu id card design software full version, drpu id card design software key, drpu id card design software free, drpu id card design software free download, drpu id.1. Field of the Invention
The present invention relates generally to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating a semiconductor device using the concept of “gate last” which makes it possible to shorten the length of the gate-structured portion of the device.
2. Description of the Prior Art
Generally, semiconductor memory devices such as dynamic random access memory (DRAM) devices include an array of memory cells for storing data. The memory cells are often arranged in rows and columns. In order to select the desired memory cell, a word line and a bit line are each coupled to the appropriate memory cell. The bit line is coupled to the memory cell in a column of the memory array, while the word line is coupled to the memory cell in a row of the memory array.
To read or write data to a selected memory cell, the bit line is charged to a high or low voltage by a bit line sense amplifier. A high voltage applied to a selected word line selects one memory cell from a memory cell array to a state such that it can be accessed by the bit line sense amplifier. A selected word line also charges a large number of memory cells in the selected row to a high voltage level. The memory cells of the selected row are thus turned on, and a “0” or “1” is stored in the selected memory cell.
The memory cells in the selected row are normally configured into flip-flop type cells as shown in FIG. 1. In particular, the memory cell includes a NMOS transistor T.sub.1 and a capacitor C.sub.1. As shown in FIG. 1, the source and drain of the NMOS transistor T.sub.1 are connected to ground, and its gate is coupled to the word line WL. The substrate potential of the NMOS transistor T.sub.1 is set at a ground voltage level by a substrate bias generator (not shown). The capacitor C.sub.1 is coupled between the drain and gate of the NMOS transistor
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